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14-bit, 150 msps, 1.8 v analog-to-digital converter ad9254 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features 1.8 v analog supply operation 1.8 v to 3.3 v output supply snr = 71.8 dbc (72.8 dbfs) to 70 mhz input sfdr = 84 dbc to 70 mhz input low power: 430 mw @ 150 msps differential input with 650 mhz bandwidth on-chip voltage reference and sample-and-hold amplifier dnl = 0.4 lsb flexible analog input: 1 v p-p to 2 v p-p range offset binary, gray code, or twos complement data format clock duty cycle stabilizer data output clock serial port control built-in selectable digital test pattern generation programmable clock and data alignment applications ultrasound equipment if sampling in communications receivers cdma2000, wcdma, td-scdma, and wimax battery-powered instruments hand-held scopemeters low cost digital oscilloscopes macro, micro, and pico cell infrastructure general description the ad9254 is a monolithic, single 1.8 v supply, 14-bit, 150 msps analog-to-digital converter (adc), featuring a high performance sample-and-hold amplifier (sha) and on-chip voltage reference. the product uses a multistage differential pipeline architecture with output error correction logic to provide 14-bit accuracy at 150 msps data rates and guarantees no missing codes over the full operating temperature range. the wide bandwidth, truly differential sha allows a variety of user-selectable input ranges and offsets, including single-ended applications. it is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the nyquist rate. combined with power and cost savings over previously available adcs, the ad9254 is suitable for applications in communications, imaging, and medical ultrasound. a differential clock input controls all internal conversion cycles. a duty cycle stabilizer (dcs) compensates for wide variations in the clock duty cycle while maintaining excellent overall adc performance. functional block diagram drvdd a vdd agnd 0.5v clk? pdwn drgnd or vin+ vin? reft refb ad9254 vref sense sha a/d mdac1 4 8 15 3 a/d 8-stage 1 1/2-bit pipeline ref select clk+ clock duty cycle stabilizer mode select correction logic output buffers dco sclk/dfs sdio/dcs csb d13 (msb) d0 (lsb) 06216-001 figure 1. the digital output data is presented in offset binary, gray code, or twos complement formats. a data output clock (dco) is provided to ensure proper latch timing with receiving logic. the ad9254 is available in a 48-lead lfcsp_vq and is specified over the industrial temperature range (?40c to +85c). product highlights 1. the ad9254 operates from a single 1.8 v power supply and features a separate digital output driver supply to accommodate 1.8 v to 3.3 v logic families. 2. the patented sha input maintains excellent performance for input frequencies up to 225 mhz. 3. the clock dcs maintains overall adc performance over a wide range of clock pulse widths. 4. a standard serial port interface supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock dcs, power-down, and voltage reference mode. 5. the ad9254 is pin-compatible with the ad9233, allowing a simple migration from 12 bits to 14 bits.
ad9254 rev. 0 | page 2 of 40 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 dc specifications ......................................................................... 3 ac specifications.......................................................................... 4 digital specifications ................................................................... 5 switching specifications .............................................................. 6 timing diagram ........................................................................... 6 absolute maximum ratings............................................................ 7 thermal resistance ...................................................................... 7 esd caution.................................................................................. 7 pin configuration and function descriptions............................. 8 equivalent circuits ........................................................................... 9 typical performance characteristics ........................................... 10 theory of operation ...................................................................... 14 analog input considerations.................................................... 14 differential input configurations ............................................ 15 voltage reference ....................................................................... 16 clock input considerations ...................................................... 17 jitter considerations .................................................................. 19 power dissipation and standby mode..................................... 19 digital outputs ........................................................................... 20 timing ......................................................................................... 20 serial port interface (spi).............................................................. 21 configuration using the spi..................................................... 21 hardware interface..................................................................... 21 configuration without the spi ................................................ 21 memory map .................................................................................. 22 reading the memory map register table............................... 22 memory map register table..................................................... 23 layout considerations................................................................... 25 power and ground recommendations ................................... 25 cml ............................................................................................. 25 rbias........................................................................................... 25 reference decoupling................................................................ 25 evaluation board ............................................................................ 26 power supplies ............................................................................ 26 input signals................................................................................ 26 output signals ............................................................................ 26 default operation and jumper selection settings................. 27 alternative clock configurations............................................ 27 alternative analog input drive configuration...................... 27 schematics................................................................................... 29 evaluation board layout........................................................... 34 bill of materials........................................................................... 37 outline dimensions ....................................................................... 40 ordering guide .......................................................................... 40 revision history 10/06revision 0: initial version
ad9254 rev. 0 | page 3 of 40 specifications dc specifications avdd = 1.8 v; drvdd = 2.5 v, maximum sample rate, 2 v p-p differential input, 1.0 v internal reference; ain = ?1.0 dbfs, dcs en abled, unless otherwise noted. table 1. ad9254bcpz-150 parameter temperature min typ max unit resolution full 14 bits accuracy no missing codes full guaranteed offset error full 0.3 0.8 % fsr gain error full 0.6 4.5 % fsr differential nonlinearity (dnl) 1 25c 0.4 lsb full 1.0 lsb integral nonlinearity (inl) 1 25c 1.5 lsb full 5.0 lsb temperature drift offset error full 15 ppm/c gain error full 95 ppm/c internal voltage reference output voltage error (1 v mode) full 5 35 mv load regulation @ 1.0 ma full 7 mv input referred noise vref = 1.0 v 25c 1.3 lsb rms analog input input span, vref = 1.0 v full 2 v p-p input capacitance 2 full 8 pf reference input resistance full 6 k power supplies supply voltage avdd full 1.7 1.8 1.9 v drvdd full 1.7 2.5 3.6 v supply current iavdd 1 full 240 260 ma idrvdd 1 (drvdd = 1.8 v) full 11 ma idrvdd 1 (drvdd = 3.3 v) full 23 ma power consumption dc input full 430 470 mw sine wave input 1 (drvdd = 1.8 v) full 450 mw sine wave input 1 (drvdd = 3.3 v) full 506 mw standby power 3 full 40 mw power-down power full 1.8 mw 1 measured with a low input frequency, full-scale sine wa ve, with approximately 5 pf load ing on each output bit. 2 input capacitance refers to the effectiv e capacitance between one differential input pin and agnd. refer to figure 4 for the e quivalent analog input structure. 3 standby power is measured with a dc input, the clk pin inactive (set to avdd or agnd).
ad9254 rev. 0 | page 4 of 40 ac specifications avdd = 1.8 v; drvdd = 2.5 v, maximum sample rate, 2 v p-p differential input, 1.0 v internal reference; ain = ?1.0 dbfs, dcs en abled, unless otherwise noted. table 2. ad9254bcpz-150 parameter 1 temperature min typ max unit signal-to-noise-ratio (snr) f in = 2.4 mhz 25c 72.0 dbc f in = 70 mhz 25c 71.8 dbc full 70.0 dbc f in = 100 mhz 25c 71.6 dbc f in = 170 mhz 25c 70.8 dbc signal-to-noise and distortion (sinad) f in = 2.4 mhz 25c 71.7 dbc f in = 70 mhz 25c 71.0 dbc full 69.0 dbc f in = 100 mhz 25c 70.6 dbc f in = 170 mhz 25c 69.8 dbc effective number of bits (enob) f in = 2.4 mhz 25c 11.7 bits f in = 70 mhz 25c 11.7 bits f in = 100 mhz 25c 11.6 bits f in = 170 mhz 25c 11.5 bits worst second or third harmonic f in = 2.4 mhz 25c ?90 dbc f in = 70 mhz 25c ?84 dbc full ?74 dbc f in = 100 mhz 25c ?83 dbc f in = 170 mhz 25c ?80 dbc spurious-free dynamic range (sfdr) f in = 2.4 mhz 25c 90 dbc f in = 70 mhz 25c 84 dbc full 74 dbc f in = 100 mhz 25c 83 dbc f in = 170 mhz 25c 80 dbc worst other (harmonic or spur) f in = 2.4 mhz 25c ?93 dbc f in = 70 mhz 25c ?93 dbc full ?85 dbc f in = 100 mhz 25c ?90 dbc f in = 170 mhz 25c ?90 dbc two-tone sfdr f in = 29 mhz (?7 dbfs ), 32 mhz (?7 dbfs ) 25c 90 dbfs f in = 169 mhz (?7 dbfs ), 172 mhz (?7 dbfs ) 25c 90 dbfs analog input bandwidth 25c 650 mhz 1 see application note an-835 , understanding high speed adc testing and evaluation , for a complete set of definitions.
ad9254 rev. 0 | page 5 of 40 digital specifications avdd = 1.8 v; drvdd = 2.5 v, maximum sample rate, 2 v p-p differential input, 1.0 v internal reference; ain = ?1.0 dbfs, dcs en abled, unless otherwise noted. table 3. ad9254bcpz-150 parameter temperature min typ max unit differential clock inputs (clk+, clk?) logic compliance cmos/lvds/lvpecl internal common-mode bias full 1.2 v differential input voltage full 0.2 6 v p-p input voltage range full avdd ? 0.3 avdd + 1.6 v input common-mode range full 1.1 avdd v high level input voltage (v ih ) full 1.2 3.6 v low level input voltage (v il ) full 0 0.8 v high level input current (i ih ) full ?10 +10 a low level input current (i il ) full ?10 +10 a input resistance full 8 10 12 k input capacitance full 4 pf logic inputs (sclk/dfs, oeb, pwdn) high level input voltage (v ih ) full 1.2 3.6 v low level input voltage (v il ) full 0 0.8 v high level input current (i ih ) full ?50 ?75 a low level input current (i il ) full ?10 +10 a input resistance full 30 k input capacitance full 2 pf logic inputs (csb) high level input voltage (v ih ) full 1.2 3.6 v low level input voltage (v il ) full 0 0.8 v high level input current (i ih ) full ?10 +10 a low level input current (i il ) full +40 +135 a input resistance full 26 k input capacitance full 2 pf logic inputs (sdio/dcs) high level input voltage (v ih ) full 1.2 drvdd + 0.3 v low level input voltage (v il ) full 0 0.8 v high level input current (i ih ) full ?10 +10 a low level input current (i il ) full +40 +130 a input resistance full 26 k input capacitance full 5 pf digital outputs drvdd = 3.3 v high level output voltage (v oh , i oh = 50 a) full 3.29 v high level output voltage (v oh , i oh = 0.5 ma) full 3.25 v low level output voltage (v ol , i ol = 1.6 ma) full 0.2 v low level output voltage (v ol , i ol = 50 a) full 0.05 v drvdd = 1.8 v high level output voltage (v oh , i oh = 50 a) full 1.79 v high level output voltage (v oh , i oh = 0.5 ma) full 1.75 v low level output voltage (v ol , i ol = 1.6 ma) full 0.2 v low level output voltage (v ol , i ol = 50 a) full 0.05 v
ad9254 rev. 0 | page 6 of 40 switching specifications avdd = 1.8 v, drvdd = 2.5 v, unless otherwise noted. table 4. ad9254bcpz-150 parameter 1 temperature min typ max unit clock input parameters conversion rate, dcs enabled full 20 150 msps conversion rate, dcs disabled full 10 150 msps clk period full 6.7 ns clk pulse width high, dcs enabled full 2.0 3.3 4.7 ns clk pulse width high, dcs disabled full 3.0 3.3 3.7 ns data output parameters data propagation delay (t pd ) 2 full 3.1 3.9 4.8 ns dco propagation delay (t dco ) full 4.4 ns setup time (t s ) full 1.9 2.9 ns hold time (t h ) full 3.0 3.8 ns pipeline delay (latency) full 12 cycles aperture delay (t a ) full 0.8 ns aperture uncertainty (jitter, t j ) full 0.1 ps rms wake-up time 3 full 350 s out-of-range recovery time full 3 cycles serial port interface 4 sclk period (t clk ) full 40 ns sclk pulse width high time (t hi ) full 16 ns sclk pulse width low time (t lo ) full 16 ns sdio to sclk setup time (t ds ) full 5 ns sdio to sclk hold time (t dh ) full 2 ns csb to sclk setup time (t s ) full 5 ns csb to sclk hold time (t h ) full 2 ns 1 see application note an-835 , understanding high speed adc testing and evaluation , for a complete set of definitions. 2 output propagation delay is measured from clk 50% transition to data 50% transition, with 5 pf load. 3 wake-up time is dependent on the value of the decoupling capacitors, values shown with 0.1 f capacitor across reft and refb. 4 see figure 50 and the serial port interface (spi) section. timing diagram clk+ dco data n n+ 1 n+ 2 n+ 3 n+ 4 n+ 5 n+ 6 n+ 7 n+ 8 n ? 12 n ? 11 n ? 10 n ? 9 n ? 8 n ? 7 n ? 6 n ? 5 n ? 4 n ? 13 clk? t clk t pd t s t h t dco t clk t a 06216-002 figure 2. timing diagram
ad9254 rev. 0 | page 7 of 40 absolute maximum ratings table 5. parameter rating electrical avdd to agnd ?0.3 v to +2.0 v drvdd to dgnd ?0.3 v to +3.9 v agnd to dgnd ?0.3 v to +0.3 v avdd to drvdd ?3.9 v to +2.0 v d0 through d13 to dgnd ?0.3 v to drvdd + 0.3 v dco to dgnd ?0.3 v to drvdd + 0.3 v or to dgnd ?0.3 v to drvdd + 0.3 v clk+ to agnd ?0.3 v to +3.9 v clk? to agnd ?0.3 v to +3.9 v vin+ to agnd ?0.3 v to avdd + 0.2 v vin? to agnd ?0.3 v to avdd + 0.2 v vref to agnd ?0.3 v to avdd + 0.2 v sense to agnd ?0.3 v to avdd + 0.2 v reft to agnd ?0.3 v to avdd + 0.2 v refb to agnd ?0.3 v to avdd + 0.2 v sdio/dcs to dgnd ?0.3 v to drvdd + 0.3 v pdwn to agnd ?0.3 v to +3.9 v csb to agnd ?0.3 v to +3.9 v sclk/dfs to agnd ?0.3 v to +3.9 v oeb to agnd ?0.3 v to +3.9 v environmental storage temperature range C65c to +125c operating temperature range C40c to +85c lead temperature (soldering 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance the exposed paddle must be soldered to the ground plane for the lfcsp_vq package. soldering the exposed paddle to the customer board increases the reliability of the solder joints, maximizing the thermal capability of the package. table 6. thermal resistance package type ja jc unit 48-lead lfcsp_vq (cp-48-3) 26.4 2.4 c/w typical ja and jc are specified for a 4-layer board in still air. airflow increases heat dissipation, effectively reducing ja . in addition, metal in direct contact with the package leads from metal traces and through holes, ground, and power planes, reduces the ja . esd caution
ad9254 rev. 0 | page 8 of 40 pin configuration and fu nction descriptions 13 14 15 16 17 18 19 20 21 22 23 24 d12 d13 (msb) or drgnd drvdd sdio/dcs sclk/dfs csb agnd avdd agnd avdd 48 47 46 45 44 43 42 41 40 39 38 37 drvdd drgnd d1 d0 (lsb) dco oeb avdd agnd avdd clk? clk+ agnd 1 2 3 4 5 6 7 8 9 10 11 12 d2 d3 d4 d5 d6 d7 drgnd drvdd d8 d9 d10 d11 rbias cml avdd agnd vin? vin+ agnd reft refb vref sense 35 pdwn 36 34 33 32 31 30 29 28 27 26 25 ad9254 top view (not to scale) pin 1 indicator 06216-003 figure 3. pin configuration table 7. pin function description pin no. mnemonic description 0, 21, 23, 29, 32, 37, 41 agnd analog ground. (pin 0 is the exposed thermal pad on the bottom of the package.) 45, 46, 1 to 6, 9 to 14 d0 (lsb) to d13 (msb) data output bits. 7, 16, 47 drgnd digital output ground. 8, 17, 48 drvdd digital output driver supply (1.8 v to 3.3 v). 15 or out-of-range indicator. 18 sdio/dcs serial port interface (spi) data input/output (ser ial port mode); duty cycle stabilizer select (external pin mode). see table 10 . 19 sclk/dfs serial port interface clock (serial port mode); data format select pin (external pin mode). 20 csb serial port interface chip select (active low). see table 10 . 22, 24, 33, 40, 42 avdd analog power supply. 25 sense reference mode selection. see table 9 . 26 vref voltage reference input/output. 27 refb differential reference (?). 28 reft differential reference (+). 30 vin+ analog input pin (+). 31 vinC analog input pin (?). 34 cml common-mode level bias output. 35 rbias external bias resistor connection. a 10 k resistor must be connected between this pin and analog ground (agnd). 36 pdwn power-down function select. 38 clk+ clock input (+). 39 clkC clock input (?). 43 oeb output enable (active low). 44 dco data clock output.
ad9254 rev. 0 | page 9 of 40 equivalent circuits v in 06216-004 figure 4. equivalent analog input circuit 1.2v 10k ? 10k? c lk+ clk? avdd 06216-005 figure 5. equivalent clock input circuit s dio/dcs 1k? drvdd 06216-006 figure 6. equivalent sdio/dcs input circuit dr v dd drgnd 06216-007 figure 7. equivalent digital output circuit s clk/dfs oeb pdwn 1k? 30k ? 06216-008 figure 8. equivalent sclk/dfs, oeb, pdwn input circuit csb 1k ? 26k ? avdd 06216-009 figure 9. equivalent csb input circuit sense 1k ? 06216-010 figure 10. equivalent sense circuit v ref a v dd 6k ? 06216-011 figure 11. equivalent vref circuit
ad9254 rev. 0 | page 10 of 40 typical performance characteristics avdd = 1.8 v; drvdd = 2.5 v; maximum sample rate, dcs enabled, 1 v internal reference; 2 v p-p differential input; ain = ?1.0 d bfs; 64k sample; t a = 25c, unless otherwise noted. 0 ?120 ?100 ?80 ?60 ?40 ?20 0 18.75 37.50 56.25 75.00 amplitude (dbfs) frequency (mhz) 150msps 2.3mhz @ ?1dbfs snr = 72.0dbc (73.0dbfs) enob = 11.7 bits sfdr = 90.0dbc 06216-012 figure 12. ad9254 single-tone fft with f in = 2.3 mhz 0 ?120 ?100 ?80 ?60 ?40 ?20 0 18.75 37.50 56.25 75.00 amplitude (dbfs) frequency (mhz) 150msps 30.3mhz @ ?1dbfs snr = 71.9dbc (72.9dbfs) enob = 11.7 bits sfdr = 88dbc 06216-013 figure 13. ad9254 single-tone fft with f in = 30.3 mhz 0 ?120 ?100 ?80 ?60 ?40 ?20 0 18.75 37.50 56.25 75.00 amplitude (dbfs) frequency (mhz) 150msps 70.3mhz @ ?1dbfs snr = 71.8dbc (72.8dbfs) enob = 11.7 bits sfdr = 84dbc 06216-014 figure 14. ad9254 single-tone fft with f in = 70.3 mhz 0 ?120 ?100 ?80 ?60 ?40 ?20 0 18.75 37.50 56.25 75.00 amplitude (dbfs) frequency (mhz) 150msps 100.3mhz @ ?1dbfs snr = 71.6dbc (72.6dbfs) enob = 11.6 bits sfdr = 83dbc 06216-015 figure 15. ad9254 single-tone fft with f in = 100.3 mhz 0 ?120 ?100 ?80 ?60 ?40 ?20 0 18.75 37.50 56.25 75.00 amplitude (dbfs) frequency (mhz) 150msps 140.3mhz @ ?1dbfs snr = 71.5dbc (72.5dbfs) enob = 11.5 bits sfdr = 81dbc 06216-016 figure 16. ad9254 single-tone fft with f in = 140.3 mhz 0 ?120 ?100 ?80 ?60 ?40 ?20 0 18.75 37.50 56.25 75.00 amplitude (dbfs) frequency (mhz) 150msps 170.3mhz @ ?1dbfs snr = 70.8dbc (71.8dbfs) enob = 11.5 bits sfdr = 80dbc 06216-017 figure 17. ad9254 single-tone fft with f in = 170.3 mhz
ad9254 rev. 0 | page 11 of 40 0 ?120 ?100 ?80 ?60 ?40 ?20 0 18.75 37.50 56.25 75.00 amplitude (dbfs) frequency (mhz) 150msps 250.3mhz @ ?1dbfs snr = 69.3dbc (70.3dbfs) enob = 11.3 bits sfdr = 79dbc 06216-018 figure 18. ad9254 single-tone fft with f in = 250.3 mhz 0 ?120 ?100 ?80 ?60 ?40 ?20 0 18.75 37.50 56.25 75.00 amplitude (dbfs) frequency (mhz) 150msps f in1 = 29.1mhz @ ?7dbfs f in2 = 32.1mhz @ ?7dbfs sfdr = 83.2dbc (90.2dbfs) woimd3 = ?83.9dbc (?90.9dbfs) 06216-019 figure 19. ad9254 two-tone fft with f in1 = 29.1 mhz, f in2 = 32.1 mhz 90 85 80 75 70 65 60 04 350 300 250 200 150 10050 snr/sfdr (dbc) input frequency (mhz) 0 0 snr +25c snr ?40c snr +85c sfdr +25c sfdr ?40c sfdr +85c 06216-020 figure 20. ad9254 single-tone snr/sfdr vs. input frequency (f in ) and temperature with 2 v p-p full scale 120 100 80 60 40 20 0 ?90 0 ?20 ?10 ?30?40 ?50 ?60?70?80 snr/sfdr (dbc and dbfs) input amplitude (dbfs) snr (dbc) 85dbc reference line sfdr (dbfs) sfdr (dbc) snr (dbfs) 06216-021 figure 21. ad9254 single-tone sn r/sfdr vs. input amplitude (ain) with f in = 2.4 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?90 ?78 ?66 ?54 ?42 ?30 ?18 ?6 sfdr/worst imd3 (dbc and dbfs) input amplitude (dbfs) sfdr (?dbc) sfdr (?dbfs) worst imd3 (dbc) worst imd3 (dbfs) 06216-022 figure 22. ad9254 two-tone sfdr/imd3 vs. input amplitude (ain) with f in1 = 29.1 mhz, f in2 = 32.1 mhz 90 85 80 75 70 65 60 04 350 300 250 200 150 10050 snr/sfdr (dbc) input frequency (mhz) 0 0 snr +25c snr ?40c snr +85c sfdr +25c sfdr ?40c sfdr +85c 06216-023 figure 23. ad9254 single-tone snr/sfdr vs. input frequency (f in ) and temperature with 1 v p-p full scale
ad9254 rev. 0 | page 12 of 40 0 ?120 ?100 ?80 ?60 ?40 ?20 0 18.75 37.50 56.25 75.00 amplitude (dbfs) frequency (mhz) 150msps f in1 = 169.1mhz @ ?7dbfs f in2 = 172.1mhz @ ?7dbfs sfdr = 83dbc (90dbfs) woimd3 = ?83dbc (90dbfs) 06216-024 figure 24. ad9254 two-tone fft with f in1 = 169.1 mhz, f in2 = 172.1 mhz 95 90 85 80 75 70 65 10 150140 130 120110100 90 80 70 6050403020 snr/sfdr (dbc) clock frequency (msps) sfdr snr 06216-025 figure 25. ad9254 single-tone snr/sfdr vs. clock frequency (f clk ) with f in = 2.4 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?90 ?78 ?66 ?54 ?42 ?30 ?18 ?6 sfdr/worst imd3 (dbc and dbfs) input amplitude (dbfs) sfdr (?dbc) sfdr (?dbfs) worst imd3 (dbc) worst imd3 (dbfs) 06216-027 figure 26. ad9254 two-tone sfdr/imd3 vs. input amplitude (ain) with f in1 = 169.1 mhz, f in2 = 172.11 mhz 2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 ?2.0 0 16384 14336 12288 10240 8192 6144 4096 2048 inl error (lsb) output code 06216-031 figure 27. ad9254 inl with f in = 10.3 mhz 12000 10000 8000 6000 4000 2000 0 number of hits code 06216-032 n ? 5 n ? 4 n ? 3 n ? 2 n ? 1 n n + 1 n + 2 n + 3 n + 4 n + 5 32768 samples 1.25 lsb rms figure 28. ad9254 grounded input histogram 0 ?0.5 ?1.0 ?1.5 ?2.0 ?40?200 20406080 ?2.5 error (%fs) temperature (c) 06216-033 gain error offset error figure 29. ad9254 gain and offset vs. temperature
ad9254 rev. 0 | page 13 of 40 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 0 16384 14336 12288 10240 8192 6144 4096 2048 dnl error (lsb) otuput code 06216-034 figure 30. ad9254 dnl with f in = 10.3 mhz
ad9254 rev. 0 | page 14 of 40 theory of operation the ad9254 architecture consists of a front-end sample-and- hold amplifier (sha) followed by a pipelined switched capacitor adc. the quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. the pipeline architecture permits the first stage to operate on a new input sample, while the remaining stages operate on preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution flash adc connected to a switched capacitor dac and interstage residue amplifier (mdac). the residue amplifier magnifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate digital correction of flash errors. the last stage consists only of a flash adc. the input stage contains a differential sha that can be ac- or dc-coupled in differential or single-ended modes. the output staging block aligns the data, carries out the error correction, and passes the data to the output buffers. the output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. during power-down, the output buffers go into a high impedance state. analog input considerations the analog input to the ad9254 is a differential switched capacitor sha that has been designed for optimum performance while processing a differential input signal. the clock signal alternately switches the sha between sample mode and hold mode (see figure 31 ). when the sha is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. a small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. a shunt capacitor can be placed across the inputs to provide dynamic charging currents. this passive network creates a low- pass filter at the adc input; therefore, the precise values are dependent upon the application. in if undersampling applications, any shunt capacitors should be reduced. in combination with the driving source impedance, these capacitors would limit the input bandwidth. for more information, see application note an-742 , frequency domain response of switched-capacitor adcs ; application note an-827 , a resonant approach to interfacing amplifiers to switched- capacitor adcs ; and the analog dialogue article, transformer- coupled front-end for wideband a/d converters. vin+ vin? c pin, par c pin, par c s c s c h c h h s s s s 06216-035 figure 31. switched-c apacitor sha input for best dynamic performance, the source impedances driving vin+ and vin? should match such that common-mode settling errors are symmetrical. these errors are reduced by the common-mode rejection of the adc. an internal differential reference buffer creates two reference voltages used to define the input span of the adc core. the span of the adc core is set by the buffer to be 2 vref. the reference voltages are not available to the user. two bypass points, reft and refb, are brought out for decoupling to reduce the noise contributed by the internal reference buffer. it is recom- mended that reft be decoupled to refb by a 0.1 f capacitor, as described in the layout considerations section. input common mode the analog inputs of the ad9254 are not internally dc-biased. in ac-coupled applications, the user must provide this bias externally. setting the device such that v cm = 0.55 avdd is recommended for optimum performance; however, the device functions over a wider range with reasonable performance (see figure 30 ). an on-board common-mode voltage reference is included in the design and is available from the cml pin. optimum performance is achieved when the common-mode voltage of the analog input is set by the cml pin voltage (typically 0.55 avdd). the cml pin must be decoupled to ground by a 0.1 f capacitor, as described in the layout considerations section.
ad9254 rev. 0 | page 15 of 40 differential input configurations optimum performance is achieved by driving the ad9254 in a differential input configuration. for baseband applications, the ad8138 differential driver provides excellent performance and a flexible interface to the adc. the output common-mode voltage of the ad8138 is easily set with the cml pin of the ad9254 (see figure 32 ), and the driver can be configured in a sallen-key filter topology to provide band limiting of the input signal. avdd 1v p-p 49.9 ? 523 ? 0.1f r r c 499 ? 499 ? 499 ? ad8138 ad9254 vin+ vin? cml 06216-036 figure 32. differential input configuration using the ad8138 for baseband applications where snr is a key parameter, differential transformer coupling is the recommended input configuration (see figure 33 ). the cml voltage can be connected to the center tap of the secondary winding of the transformer to bias the analog input. the signal characteristics must be considered when selecting a transformer. most rf transformers saturate at frequencies below a few megahertz, and excessive signal power can cause core saturation, which leads to distortion. 2v p-p 49.9 ? 0.1f r r c ad9254 vin+ vin? cml 06216-037 figure 33. differential transformer-coupled configuration at input frequencies in the second nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true snr performance of the ad9254. for applications where snr is a key parameter, transformer coupling is the recommended input. for applications where sfdr is a key parameter, differential double balun coupling is the recom- mended input configuration (see figure 35 ). as an alternative to using a transformer-coupled input at frequencies in the second nyquist zone, the ad8352 differential driver can be used (see figure 36 ). in any configuration, the value of the shunt capacitor, c, is dependent on the input frequency and source impedance and may need to be reduced or removed. table 8 displays recom- mended values to set the rc network. however, these values are dependent on the input signal and should only be used as a starting guide. table 8. rc network recommended values frequency range (mhz) r series () c differential (pf) 0 to 70 33 15 70 to 200 33 5 200 to 300 15 5 >300 15 open single-ended input configuration although not recommended, it is possible to operate the ad9254 in a single-ended input configuration, as long as the input voltage swing is within the avdd supply. single-ended operation can provide adequate performance in cost-sensitive applications. in this configuration, sfdr and distortion performance degrade due to the large input common-mode swing. if the source impedances on each input are matched, there should be little effect on snr performance. figure 34 details a typical single-ended input configuration. 1v p-p r r c 49.9 ? 0.1f 10f 10f 0.1f av dd 1k? 1k ? 1k ? 1k ? ad9254 a v dd vin+ vin? 06216-038 figure 34. single-ended input configuration
ad9254 rev. 0 | page 16 of 40 ad9254 r 0.1f 0.1f 2v p-p vin+ vin? cml c r 0.1f s 0.1f 25 ? 25 ? s p a p 06216-039 figure 35. differential double balun input configuration ad9254 ad8352 0 ? r 0 ? c d r d r g 0.1f 0.1f 0.1f vin+ vin? cml c 0.1f 0.1f 16 1 2 3 4 5 11 r 0.1f 0.1f 10 8, 13 14 v cc 200 ? 200 ? 06216-040 figure 36. differential input configuration using the ad8352 table 9. reference configuration summary selected mode sense voltage resulting vref (v) resulting differential span (v p-p) external reference avdd n/a 2 external reference internal fixed reference vref 0.5 1.0 programmable reference 0.2 v to vref ? ? ? ? ? ? + 1 2 15.0 r r (see figure 38 ) 2 vref internal fixed reference agnd to 0.2 v 1.0 2.0 voltage reference a stable and accurate voltage reference is built into the ad9254. the input range is adjustable by varying the reference voltage applied to the ad9254, using either the internal reference or an externally applied reference voltage. the input span of the adc tracks reference voltage changes linearly. the various reference modes are summarized in the following sections. the reference decoupling section describes the best practices and require- ments for pcb layout of the reference. internal reference connection a comparator within the ad9254 detects the potential at the sense pin and configures the reference into four possible states, as summarized in table 9 . if sense is grounded, the reference amplifier switch is connected to the internal resistor divider (see figure 37 ), setting vref to 1 v. connecting the sense pin to vref switches the reference amplifier input to the sense pin, completing the loop and providing a 0.5 v reference output. if a resistor divider is connected external to the chip, as shown in figure 38 , the switch sets to the sense pin. this puts the reference amplifier in a noninverting mode with the vref output defined as ? ? ? ? ? ? += 15.0 if the sense pin is connected to avdd, the reference amplifier is disabled, and an external reference voltage can be applied to the vref pin (see the external reference operation section). the input range of the adc always equals twice the voltage at the reference pin for either an internal or an external reference.
ad9254 rev. 0 | page 17 of 40 vref sense 0.5v ad9254 reft refb select logic 0.1f 0.1f 0.1f vin? vin+ adc core ? ? 06216-041 figure 37. internal reference configuration vref sense 0.5v ad9254 vin? vin+ reft refb select logic 0.1f 0.1f r2 r1 0.1f adc core ? ? 06216-042 figure 38. programmable reference configuration if the internal reference of the ad9254 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. figure 39 depicts how the internal reference voltage is affected by loading. 0 ?1.25 02.0 load current (ma) reference voltage error (%) ?0.25 ?0.50 ?0.75 ?1.00 0.5 1.0 1.5 vref = 0.5v vref = 1v 06216-043 figure 39. vref accuracy vs. load external reference operation the use of an external reference may be necessary to enhance the gain accuracy of the adc or improve thermal drift characteristics. figure 40 shows the typical drift characteristics of the internal reference in both 1 v and 0.5 v modes. ?40 ?20 10 0 temperature (c) reference voltage error (mv) 8 6 4 2 80 0 204060 vref = 1v vref = 0.5v 06216-044 figure 40. typical vref drift when the sense pin is tied to avdd, the internal reference is disabled, allowing the use of an external reference. an internal resistor divider loads the external reference with an equivalent 6 k load (see figure 11). in addition, an internal buffer generates the positive and negative full-scale references for the adc core. therefore, the external reference must be limited to a maximum of 1 v. clock input considerations for optimum performance, the ad9254 sample clock inputs (clk+ and clk?) should be clocked with a differential signal. the signal is typically ac-coupled into the clk+ pin and the clk? pin via a transformer or capacitors. these pins are biased internally (see figure 5) and require no external bias. clock input options the ad9254 has a very flexible clock input structure. the clock input can be a cmos, lvds, lvpecl, or sine wave signal. regardless of the type of signal used, the jitter of the clock source is of the most concern, as described in the jitter considerations section. figure 41 shows one preferred method for clocking the ad9254. a low jitter clock source is converted from single- ended to a differential signal using an rf transformer. the back-to-back schottky diodes across the transformer secondary limit clock excursions into the ad9254 to approximately 0.8 v p-p differential. this helps prevent the large voltage swings of the clock from feeding through to other portions of the ad9254, while preserving the fast rise and fall times of the signal, which are critical to a low jitter performance.
ad9254 rev. 0 | page 18 of 40 0.1f 0.1f 0.1f 0.1f schottky diodes: hms2812 cloc k input 50? 100 ? clk? clk+ adc ad9254 mini-circuits adt1?1wt, 1:1z xfmr 06216-045 figure 41. transformer coupled differential clock if a low jitter clock source is not available, another option is to ac-couple a differential pecl signal to the sample clock input pins as shown in figure 42 . the ad9510 / ad9511 / ad9512 / ad9513 / ad9514 / ad9515 family of clock drivers offers excellent jitter performance. 100 ? 0.1f 0.1f 0.1f 0.1f 240 ? 240 ? ad951x pecl driver 50 ? 1 50 ? 1 clk clk 1 50 ? resistors are optional. clk? clk+ adc ad9254 clock input clock input 06216-046 figure 42. differential pecl sample clock a third option is to ac-couple a differential lvds signal to the sample clock input pins, as shown in figure 43 . the ad9510 / ad9511 / ad9512 / ad9513 / ad9514 / ad9515 family of clock drivers offers excellent jitter performance. 100 ? 0.1f 0.1f 0.1f 0.1f 50 ? 1 ad951x lvds driver 50? 1 clk clk 1 50? resistors are optional. clk? clk+ clock input clock input adc ad9254 06216-047 figure 43. differential lvds sample clock in some applications, it is acceptable to drive the sample clock inputs with a single-ended cmos signal. in such applications, directly drive clk+ from a cmos gate, while bypassing the clk? pin to ground using a 0.1 f capacitor in parallel with a 39 k resistor (see figure 44 ). clk+ can be directly driven from a cmos gate. this input is designed to withstand input voltages up to 3.6 v, making the selection of the drive logic voltage very flexible. when driving clk+ with a 1.8 v cmos signal, biasing the clk? pin with a 0.1 f capacitor in parallel with a 39 k resistor (see figure 44 ) is required. the 39 k resistor is not required when driving clk+ with a 3.3 v cmos signal (see figure 45 ). optional 100 ? 0.1f 0.1f 0.1f 39 k ? ad951x cmos driver 50 ? 1 1 50 ? resistor is optional. clk? clk+ adc ad9254 vcc 1k? 1k? clock input 06216-048 figure 44. single-ended 1.8 v cmos sample clock 1 50 ? resistor is optional. optional 100 ? 0.1f 0.1f 0.1f vcc ad951x cmos driver 50 ? 1 clk? clk+ adc ad9254 1k? 1k? clock input 06216-049 figure 45. single-ended 3.3 v cmos sample clock clock duty cycle typical high speed adcs use both clock edges to generate a variety of internal timing signals. as a result, these adcs may be sensitive to clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. the ad9254 contains a duty cycle stabilizer (dcs) that retimes the nonsampling, or falling edge, providing an internal clock signal with a nominal 50% duty cycle. this allows a wide range of clock input duty cycles without affecting the performance of the ad9254. noise and distortion performance are nearly flat for a wide range of duty cycles when the dcs is on, as shown in figure 28 . jitter in the rising edge of the input is still of paramount concern and is not reduced by the internal stabilization circuit. the duty cycle control loop does not function for clock rates less than 20 mhz nominally. the loop has a time constant associated with it that needs to be considered in applications where the clock rate can change dynamically. this requires a wait time of 1.5 s to 5 s after a dyna mic clock frequency increase (or decrease) before the dcs loop is relocked to the input signal. during the time period the loop is not locked, the dcs loop is bypassed, and the internal device timing is dependent on the duty cycle of the input clock signal. in such an application, it may be appropriate to disable th e duty cycle stabilizer. in all other applications, enabling the dcs circuit is recommended to maximize ac performance.
ad9254 rev. 0 | page 19 of 40 the dcs can be enabled or disabled by setting the sdio/dcs pin when operating in the external pin mode (see table 10), or via the spi, as described in table 13. table 10. mode selection (external pin mode) voltage at pin sclk/dfs sdio/dcs agnd binary (default) dcs disabled avdd twos complement dcs enabled (default) jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given input frequency (f in ) due to jitter (t j ) is calculated as follows: snr = ?20 log (2 f in t j ) in the equation, the rms aperture jitter represents the root mean square of all jitter sources, which include the clock input, analog input signal, and adc aperture jitter specification. if under- sampling applications are particularly sensitive to jitter, as shown in figure 46. 75 70 65 60 55 50 45 40 1 10 100 1000 snr (dbc) input frequency (mhz) 3.00ps 0.05ps measured performance 0.20ps 0.5ps 1.0ps 1.50ps 2.00ps 2.50ps 06216-050 figure 46. snr vs. input frequency and jitter treat the clock input as an analog signal in cases where aperture jitter can affect the dynamic range of the ad9254. power supplies for clock drivers should be separated from the adc output driver supplies to avoid modulating the clock signal with digital noise. the power supplies should also not be shared with analog input circuits, such as buffers, to avoid the clock modulating onto the input signal or vice versa. low jitter, crystal-controlled oscil- lators make the best clock sources. if the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. refer to application notes an-501 , aperture uncertainty and adc system performance ; and an-756, sampled systems and the effects of clock phase noise and jitter , for more in-depth information about jitter performance as it relates to adcs. power dissipation and standby mode the power dissipated by the ad9254 is proportional to its sample rate (see figure 47). the digital power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. maximum drvdd current (i drvdd ) can be calculated as n f c v i clk load drvdd drvdd = 2 where n is the number of output bits, 14 in the ad9254. this maximum current occurs when every output bit switches on every clock cycle, that is, a full-scale square wave at the nyquist frequency, f clk /2. in practice, the drvdd current is established by the average number of output bits switching, which is determined by the sample rate and the characteristics of the analog input signal. reducing the capacitive load presented to the output drivers can minimize digital power consumption. the data in figure 47 was taken under the same operating conditions as the data for the typical performance characteristics section, with a 5 pf load on each output driver. 06216-051 500 480 460 440 420 400 380 360 340 320 300 300 250 200 150 100 50 0 0 102030405060708090100110120130140150 power (mw) current (ma) clock frequency (mhz) power i (avdd) i (drvdd) figure 47. ad9254 power and current vs. clock frequency f in = 30 mhz power-down mode by asserting the pdwn pin high, the ad9254 is placed in power- down mode. in this state, the adc typically dissipates 1.8 mw. during power-down, the output drivers are placed in a high impedance state. reasserting the pdwn pin low returns the ad9254 to its normal operational mode. this pin is both 1.8 v and 3.3 v tolerant. low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. the decoupling capacitors on reft and refb are discharged when entering power-down mode and then must be recharged when returning to normal operation. as a result, the wake-up time is related to the time spent in power-down mode; and shorter power-down cycles result in proportionally shorter wake-up times. with the recommended 0.1 f decoupling capaci- tors on reft and refb, it takes approximately 0.25 ms to fully discharge the reference buffer decoupling capacitors and 0.35 ms to restore full operation.
ad9254 rev. 0 | page 20 of 40 standby mode when using the spi port interface, the user can place the adc in power-down or standby modes. standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required (see the memory map section). digital outputs the ad9254 output drivers can be configured to interface with 1.8 v to 3.3 v logic families by matching drvdd to the digital supply of the interfaced logic. the output drivers are sized to provide sufficient output current to drive a wide variety of logic families. however, large drive currents tend to cause current glitches on the supplies that may affect converter performance. applications requiring the adc to drive large capacitive loads or large fan-outs may require external buffers or latches. the output data format can be selected for either offset binary or twos complement by setting the sclk/dfs pin when operat- ing in the external pin mode (see table 10). as detailed in the interfacing to high speed adcs via spi user manual , the data format can be selected for either offset binary, twos complement, or gray code when using the spi control. out-of-range (or) condition an out-of-range condition exists when the analog input voltage is beyond the input range of the adc. or is a digital output that is updated along with the data output corresponding to the particular sampled input voltage. thus, or has the same pipeline latency as the digital data. 1 0 0 0 0 1 or data outputs or +fs ? 1 lsb +fs ? 1/2 lsb +fs ?fs ?fs + 1/2 lsb ?fs ? 1/2 lsb 1111 1111 1111 1111 1111 1111 1111 1111 1110 0000 0000 0000 11 11 11 00 00 00 0000 0000 0000 0001 0000 0000 06216-052 figure 48. or relation to input voltage and output data or is low when the analog input voltage is within the analog input range and high when the analog input voltage exceeds the input range, as shown in figure 48. or remains high until the analog input returns to within the input range and another conversion is completed. by logically anding the or bit with the msb and its complement, overrange high or underrange low conditions can be detected. table 11 is a truth table for the overrange/underrange circuit in figure 49, which uses nand gates. msb or msb over = 1 under = 1 06216-053 figure 49. overrange/underrange logic table 11. overrange/underrange truth table or msb analog input is: 0 0 within range 0 1 within range 1 0 underrange 1 1 overrange digital output enable function (oeb) the ad9254 has three-state ability. if the oeb pin is low, the output data drivers are enabled. if the oeb pin is high, the output data drivers are placed in a high impedance state. this is not intended for rapid access to the data bus. note that oeb is referenced to the digital supplies (drvdd) and should not exceed that supply voltage. timing the lowest typical conversion rate of the ad9254 is 10 msps. at clock rates below 10 msps, dynamic performance can degrade. the ad9254 provides latched data outputs with a pipeline delay of twelve clock cycles. data outputs are available one propaga- tion delay (t pd ) after the rising edge of the clock signal. the length of the output data lines and the loads placed on them should be minimized to reduce transients within the ad9254. these transients can degrade the dynamic performance of the converter. data clock output (dco) the ad9254 also provides data clock output (dco) intended for capturing the data in an external register. the data outputs are valid on the rising edge of dco, unless the dco clock polarity has been changed via the spi. see figure 2 for a graphical timing description. table 12. output data format input (v) condition (v) binary output mode twos complement mode gray code mode (spi accessible) or vin+ C vinC < Cvref C 0.5 lsb 00 0000 0000 0000 10 0000 0000 0000 11 0000 0000 0000 1 vin+ C vinC = Cvref 00 0000 0000 0000 10 0000 0000 0000 11 0000 0000 0000 0 vin+ C vinC = 0 10 0000 0000 0000 00 0000 0000 0000 00 0000 0000 0000 0 vin+ C vinC = +vref C 1.0 lsb 11 1111 1111 1111 01 1111 1111 1111 10 0000 0000 0000 0 vin+ C vinC > +vref C 0.5 lsb 11 1111 1111 1111 01 1111 1111 1111 10 0000 0000 0000 1
ad9254 rev. 0 | page 21 of 40 serial port interface (spi) the ad9254 serial port interface (spi) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the adc. this provides the user added flexibility and customization depending on the application. addresses are accessed via the serial port and may be written to or read from via the port. memory is organized into bytes that are further divided into fields, as documented in the memory map section. for detailed operational information, see the interfacing to high speed adcs via spi user manual . configuration using the spi as summarized in table 13, three pins define the spi of this adc. the sclk/dfs pin synchronizes the read and write data presented to the adc. the sdio/dcs dual-purpose pin allows data to be sent to and read from the internal adc memory map registers. the csb pin is an active low control that enables or disables the read and write cycles. table 13. serial port interface pins pin name function sclk/dfs sclk (serial clock) is the serial shift clock in. sclk synchronizes serial interface reads and writes. sdio/dcs sdio (serial data input/ output) is a dual-purpose pin. the typical role for this pin is an input and output, depending on the instruction being sent and the relative position in the timing frame. csb csb (chip select bar) is an active-low control that gates the read and write cycles. the falling edge of the csb in conjunction with the rising edge of the sclk determines the start of the framing. figure 50 and table 14 provide examples of the serial timing and its definitions. other modes involving the csb are available. the csb can be held low indefinitely to permanently enable the device (this is called streaming). the csb can stall high between bytes to allow for additional external timing. when csb is tied high, spi functions are placed in a high impedance mode. this mode turns on any spi pin secondary functions. during an instruction phase, a 16-bit instruction is transmitted. data follows the instruction phase and the length is determined by the w0 bit and the w1 bit. all data is composed of 8-bit words. the first bit of each individual byte of serial data indicates whether a read or write command is issued. this allows the serial data input/output (sdio) pin to change direction from an input to an output. in addition to word length, the instruction phase determines if the serial frame is a read or write operation, allowing the serial port to be used to both program the chip as well as read the contents of the on-chip memory. if the instruction is a readback operation, performing a readback causes the serial data input/output (sdio) pin to change direction from an input to an output at the appropriate point in the serial frame. data can be sent in msb- or in lsb-first mode. msb first is the default on power-up and can be changed via the configuration register. for more information, see the interfacing to high speed adcs via spi user manual. table 14. spi timing diagram specifications name description t ds setup time between data and rising edge of sclk t dh hold time between data and rising edge of sclk t clk period of the clock t s setup time between csb and sclk t h hold time between csb and sclk t hi minimum period that sclk should be in a logic high state t lo minimum period that sclk should be in a logic low state hardware interface the pins described in table 13 comprise the physical interface between the users programming device and the serial port of the ad9254. the sclk and csb pins function as inputs when using the spi interface. the sdio pin is bidirectional, functioning as an input during write phases and as an output during readback. the spi interface is flexible enough to be controlled by either prom or pic microcontrollers. this provides the user with the ability to use an alternate method to program the adc. one method is described in detail in application note an-812 , microcontroller-based serial port interface boot circuit . when the spi interface is not used, some pins serve a dual function. when strapped to avdd or ground during device power on, the pins are associated with a specific function. configuration without the spi in applications that do not interface to the spi control registers, the sdio/dcs and sclk/dfs pins serve as stand-alone cmos-compatible control pins. when the device is powered up, it is assumed that the user intends to use the pins as static control lines for the output data format and duty cycle stabilizer (see table 10). in this mode, the csb chip select should be connected to avdd, which disables the serial port interface. for more information, see the interfacing to high speed adcs via spi user manual.
ad9254 rev. 0 | page 22 of 40 memory map reading the memory map register table each row in the memory map register table has eight address locations. the memory map is roughly divided into three sections: the chip configuration registers map (address 0x00 to address 0x02), the device index and transfer registers map (address 0xff), and the adc functions map (address 0x08 to address 0x18). table 15 displays the register address number in hexadecimal in the first column. the last column displays the default value for each hexadecimal address. the bit 7 (msb) column is the start of the default hexadecimal value given. for example, hexadecimal address 0x14, output_phase, has a hexadecimal default value of 0x00. this means bit 3 = 0, bit 2 = 0, bit 1 = 1, and bit 0 = 1 or 0011 in binary. this setting is the default output clock or dco phase adjust option. the default value adjusts the dco phase 90 relative to the nominal dco edge and 180 relative to the data edge. for more information on this function, consult the interfacing to high speed adcs via spi user manual. open locations locations marked as open are currently not supported for this device. when required, these locations should be written with 0s. writing to these locations is required only when part of an address location is open (for example, address 0x14). if the entire address location is open (address 0x13), then the address location does not need to be written. default values coming out of reset, critical registers are loaded with default values. the default values for the registers are shown in table 15. logic levels an explanation of two registers follows: ? bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. ? clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit. spi-accessible features a list of features accessible via the spi and a brief description of what the user can do with these features follows. these features are described in detail in the interfacing to high speed adcs via spi user manual. ? modes: set either power-down or standby mode. ? clock: access the dcs via the spi. ? offset: digitally adjust the converter offset. ? te s t i / o : set test modes to have known data on output bits. ? output mode: setup outputs, vary the strength of the output drivers. ? output phase: set the output clock polarity. ? vref: set the reference voltage. don?t care don?t care don?t care don?t care sdio sclk csb t s t dh t hi t clk t lo t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 06216-054 figure 50. serial port interface timing diagram
ad9254 rev. 0 | page 23 of 40 memory map register table table 15. memory map register addr. (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments chip configuration registers 00 chip_port_config 0 lsb first 0 = off (default) 1 = on soft reset 0 = off (default) 1 = on 1 1 soft reset 0 = off (default) 1 = on lsb first 0 = off (default) 1 = on 0 0x18 the nibbles should be mirrored. see the interfacing to high speed adcs via spi user manual. 01 chip_id 8-bit chip id bits 7:0 (ad9254 = 0x00), (default) read only default is unique chip id, different for each device. 02 chip_grade open open open open child id 0 = 150 msps open open open read only child id used to differentiate speed grades. device index and transfer registers ff device_update open open open open open open open sw transfer 0x00 synchronously transfers data from the master shift register to the slave. global adc functions 08 modes open open pdwn 0full 1 standby open open internal power-down mode 000normal (power-up) 001full power-down 010standby 011normal (power-up) note: external pdwn pin overrides this setting. 0x00 determines various generic modes of chip operation. see the power dissipation and standby mode and the spi- accessible features sections. 09 clock open open open open open open open duty cycle stabilizer 0 disabled 1 enabled 0x01 see the clock duty cycle section and the spi-accessible features section.
ad9254 rev. 0 | page 24 of 40 addr. (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments flexible adc functions 10 offset digital offset adjust<5:0> 011111 011110 011101 000010 000001 000000 111111 111110 111101 ... 100001 100000 offset in lsbs +31 +30 +29 +2 +1 0 (default) 1 ?2 ?3 ?31 ?32 0x00 adjustable for offset inherent in the converter. see spi- accessible features section. 0d test_io pn23 0 = normal (default) 1 = reset pn9 0 = normal (default) 1 = reset global output test options 000off 001midscale short 010+fs short 011?fs short 100checker board output 101pn 23 sequence 110pn 9 111one/zero word toggle 0x00 see the interfacing to high speed adcs via spi user manual. 14 output_mode output driver configuration 00 for drvdd = 2.5 v to 3.3 v 10 for drvdd = 1.8 v open output disable 1 disabled 0 enabled 1 open output data invert 1 = invert data format select 00offset binary (default) 01twos complement 10gray code 0x00 configures the outputs and the format of the data. 16 output_phase output clock polarity 1 = inverted 0 = normal (default) open open open open open open open 0x00 see the spi- accessible features section. 18 vref internal reference resistor divider 00vref = 1.25 v 01vref = 1.5 v 10vref = 1.75 v 11vref = 2.00 v (default) open open open open open open 0xc0 see the spi- accessible features section. 1 external output enable (oeb) pin must be high.
ad9254 rev. 0 | page 25 of 40 layout considerations power and ground recommendations when connecting power to the ad9254, it is recommended that two separate supplies be used: one for analog (avdd, 1.8 v nominal) and one for digital (drvdd, 1.8 v to 3.3 v nominal). if only a single 1.8 v supply is available, it is routed to avdd first, then tapped off and isolated with a ferrite bead or filter choke with decoupling capacitors proceeding connection to drvdd. the user can employ several different decoupling capacitors to cover both high and low frequencies. these should be located close to the point of entry at the pc board level and close to the parts with minimal trace length. a single pc board ground plane is sufficient when using the ad9254. with proper decoupling and smart partitioning of analog, digital, and clock sections of the pc board, optimum performance is easily achieved. exposed paddle thermal heat slug recommendations it is required that the exposed paddle on the underside of the adc be connected to analog ground (agnd) to achieve the best electrical and thermal performance of the ad9254. an exposed, continuous copper plane on the pcb should mate to the ad9254 exposed paddle, pin 0. the copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the pcb. these vias should be solder-filled or plugged. to maximize the coverage and adhesion between the adc and pcb, partition the continuous plane by overlaying a silkscreen on the pcb into several uniform sections. this provides several tie points between the two during the reflow process. using one continuous plane with no partitions guarantees only one tie point between the adc and pcb. see figure 51 for a pcb layout example. for detailed information on packaging and the pcb layout of chip scale packages, see application note an-772 , a design and manufacturing guide for the lead frame chip scale package . silkscreen p a rtition pin 1 indicator 06216-055 figure 51. typical pcb layout cml the cml pin should be decoupled to ground with a 0.1 f capacitor, as shown in figure 33 . rbias the ad9254 requires the user to place a 10 k resistor between the rbias pin and ground. this resister sets the master current reference of the adc core and should have at least a 1% tolerance. reference decoupling the vref pin should be externally decoupled to ground with a low esr 1.0 f capacitor in parallel with a 0.1 f ceramic low esr capacitor. in all reference configurations, reft and refb are bypass points provided for reducing the noise contributed by the internal reference buffer. it is recommended that an external 0.1 f ceramic capacitor be placed across reft/refb. while placement of this 0.1 f capacitor is not required, the snr performance degrades by approximately 0.1 db without it. all reference decoupling capacitors should be placed as close to the adc as possible with minimal trace lengths.
ad9254 rev. 0 | page 26 of 40 evaluation board the ad9254 evaluation board provides all of the support circuitry required to operate the adc in its various modes and configu- rations. the converter can be driven differentially through a double balun configuration (default) or through the ad8352 differential driver. the adc can also be driven in a single-ended fashion. separate power pins are provided to isolate the dut from the ad8352 drive circuitry. each input configuration can be selected by proper connection of various components (see figure 53 to figure 63 ). figure 52 shows the typical bench characterization setup used to evaluate the ac performance of the ad9254. it is critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the converter. proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is also necessary to achieve the specified noise performance. see figure 53 to figure 57 for the complete schematics and layout diagrams that demonstrate the routing and grounding techniques that should be applied at the system level. power supplies this evaluation board comes with a wall-mountable switching power supply that provides a 6 v, 2 a maximum output. connect the supply to the rated 100 v ac to 240 v ac wall outlet at 47 hz to 63 hz. the other end is a 2.1 mm inner diameter jack that connects to the pcb at p500. once on the pc board, the 6 v supply is fused and conditioned before connecting to five low dropout linear regulators that supply the proper bias to each of the various sections on the board. when operating the evaluation board in a nondefault condition, l501, l503, l504, l508, and l509 can be removed to disconnect the switching power supply. this enables the user to individually bias each section of the board. use p501 to connect a different supply for each section. at least one 1.8 v supply is needed with a 1 a current capability for avdd_dut and drvdd_dut; however, it is recommended that separate supplies be used for analog and digital. to operate the evaluation board using the ad8352 option, a separate 5.0 v supply (amp_vdd) with a 1 a current capability is needed. to operate the evaluation board using the alternate spi options, a separate 3.3 v analog supply is needed, in addition to the other supplies. the 3.3 v supply (avdd_3.3v) should have a 1 a current capability as well. solder jumpers j501, j502, and j505 allow the user to combine these supplies (see figure 57 for more details). input signals when connecting the clock and analog source, use clean signal generators with low phase noise, such as rohde & schwarz smhu or agilent hp8644 signal generators or the equivalent. use one meter long, shielded, rg-58, 50 coaxial cable for making connections to the evaluation board. enter the desired frequency and amplitude for the adc. typically, most evaluation boards from analog devices, inc. can accept a ~2.8 v p-p or 13 dbm sine wave input for the clock. when connecting the analog input source, it is recommended to use a multipole, narrow- band, band-pass filter with 50 terminations. analog devices uses tte?, allen avionics, and k&l? types of band-pass filters. connect the filter directly to the evaluation board, if possible. output signals the parallel cmos outputs interface directly with the analog devices standard single-channel fifo data capture board (hsc-adc-evalb-sc). for more information on the fifo boards and their optional settings, visit www.analog.com/fifo . rohde & schwarz, smhu, 2v p-p signal synthesizer rohde & schwarz, smhu, 2v p-p signal synthesizer band-pass filter ain clk 14-bit parallel cmos usb connection ad9254 evaluation board hsc-adc-evalb-sc fifo data capture board pc running adc analyzer and spi user software 1.8v ?+ ?+ avdd_dut vdl drvdd_dut gnd gnd ?+ 5.0v gnd amp_vdd 2.5v 6v dc 2a max wall outlet 100v to 240v ac 47hz to 63hz switching power supply ?+ gnd 3.3v avdd_3.3v ?+ gnd 3.3v ?+ vcc gnd 3.3v spi spi spi 06216-056 figure 52. evaluation board connection
ad9254 rev. 0 | page 27 of 40 default operation and jumper selection settings the following is a list of the default and optional settings or modes allowed on the ad9254 rev. a evaluation board. power connect the switching power supply that is supplied in the evaluation kit between a rated 100 v ac to 240 v ac wall outlet at 47 hz to 63 hz and p500. vin the evaluation board is set up for a double balun configuration analog input with optimum 50 impedance matching out to 70 mhz. for more bandwidth response, the differential capacitor across the analog inputs can be changed or removed (see table 8). the common mode of the analog inputs is developed from the center tap of the transformer via the cml pin of the adc (see the analog input considerations section). vref vref is set to 1.0 v by tying the sense pin to ground via jp507 (pin 1 and pin 2). this causes the adc to operate in 2.0 v p-p full-scale range. a separate external reference option is also included on the evaluation board. connect jp507 between pin 2 and pin 3, connect jp501, and provide an external reference at e500. proper use of the vref options is detailed in the voltage reference section. rbias rbias requires a 10 k resistor (r503) to ground and is used to set the adc core bias current. clock the default clock input circuitry is derived from a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (t503) that adds a very low amount of jitter to the clock path. the clock input is 50 terminated and ac-coupled to handle single-ended sine wave inputs. the transformer converts the single-ended input to a differential signal that is clipped before entering the adc clock inputs. pdwn to enable the power-down feature, connect jp506, shorting the pdwn pin to avdd. csb the csb pin is internally pulled-up, setting the chip into external pin mode, to ignore the sdio and sclk information. to connect the control of the csb pin to the spi circuitry on the evaluation board, connect jp1 pin 1 and pin 2. to set the chip into serial pin mode, and enable the spi information on the sdio and sclk pins, tie jp1 low (connect pin 2 and pin 3) in the always enabled mode. sclk/dfs if the spi port is in external pin mode, the sclk/dfs pin sets the data format of the outputs. if the pin is left floating, the pin is internally pulled down, setting the default condition to binary. connecting jp2 pin 2 and pin 3 sets the format to twos comple- ment. if the spi port is in serial pin mode, connecting jp2 pin 1 and pin 2 connects the sclk pin to the on-board spi circuitry (see the serial port interface (spi) section). sdio/dcs if the spi port is in external pin mode, the sdio/dcs pin acts to set the duty cycle stabilizer. if the pin is left floating, the pin is internally pulled up, setting the default condition to dcs enabled. to disable the dcs, connect jp3 pin 2 and pin 3. if the spi port is in serial pin mode, connecting jp3 pin 1 and pin 2 connects the sdio pin to the on-board spi circuitry (see the serial port interface (spi) section). alternative clock configurations a differential lvpecl clock can also be used to clock the adc input using the ad9515 (u500). when using this drive option, the components listed in table 16 need to be populated. consult the ad9515 data sheet for further information. to configure the analog input to drive the ad9515 instead of the default transformer option, the following components need to be added, removed, and/or changed. 1. remove r507, r508, c532, and c533 in the default clock path. 2. populate r505 with a 0 resistor and c531 in the default clock path. 3. populate r511, r512, r513, r515 to r524, u500, r580, r582, r583, r584, c536, c537, and r586. if using an oscillator, two oscillator footprint options are also available (osc500) to check the performance of the adc. jp508 provides the user flexibility in using the enable pin, which is common on most oscillators. populate osc500, r575, r587, and r588 to use this option. alternative analog input drive configuration this section provides a brief description of the alternative analog input drive configuration using the ad8352 . when using this particular drive option, some components need to be populated, as listed in table 16. for more details on the ad8352 differential driver, including how it works and its optional pin settings, consult the ad8352 data sheet.
ad9254 rev. 0 | page 28 of 40 to configure the analog input to drive the ad8352 instead of the default transformer option, the following components need to be added, removed, and/or changed: 1. remove c1 and c2 in the default analog input path. 2. populate r3 and r4 with 200 resistors in the analog input path. 3. populate the optional amplifier input path with all components except r594, r595, and c502. note that to terminate the input path, only one of the following components should be populated: r9, r592, or the combination of r590 and r591). 4. populate c529 with a 5 pf capacitor in the analog input path. currently, r561 and r562 are populated with 0 resistors to allow signal connection. this area allows the user to design a filter if additional requirements are necessary.
ad9254 rev. 0 | page 29 of 40 schematics dni rc0603 rc0603 rc0603 cc0402 smaedge smaedge cc0402 cc0402 etc1-1-13 sp r c 0402 rc0402 rc0402 rc040 2 rc040 2 rc0402 rc0402 rc0402 rc0402 rc0402 rc0402 rc0402 rc0402 rc060 3 rc0402 etc1-1-13 sp sp sma200up sma200up r590/r591,r9,r592 only one s hould be installed at a time. double balun / xfmr input dni dni dni dni dni dni dni dni dni dni when using r1, remove r3, r4,r6. replace c1, c2 with 0 ohm resistors. for amplifier (ad8352): when using t502, remove t500, t501. repalce c1, c2 with 0 ohm resistors. optional amp input ain ain/ ampin ampin/ gnd;3,4,5 s505 dni s504 gnd;3,4,5 dni 5 43 2 1 t1 dni 1 2 3 4 5 t500 50 r502 dni r1 r8 dni 9 12 67 15 4 1 3 2 8 13 5 16 14 10 11 u511 signal=gnd;17 r536 0 r593 2 3 1 j500 r594 10k r595 10k 0 r5 r563 dni r566 33 33 r567 r574 dni 0 r562 r561 0 0 r571 25 r3 r4 25 dni r565 0 r2 dni r6 4.3k r597 r590 25 25 r591 r592 r596 r598 100 2 1 3 5 4 t501 1 3 2 d501 hsms281 2 dni 1 3 2 d500 hsms281 2 dni 1 34 6 25 t502 cml .1uf c510 cml 0.3pf c501 c509 .1uf c503 .1uf 0.1uf c528 vin+ dutavdd vin- vin+ .1uf c1 .1uf c2 .1uf c500 20pf c529 c505 .1uf .1uf c504 .1uf c502 vin- dutavdd ampout+ ampout- cml ampvdd ampvdd ampvdd ampout+ ampout- 0 r535 gnd;3,4,5 s500 s503 gnd;3,4,5 c3 dni 12 dni r7 12 r560 0 2 1 r10 0 0 c4 dni r9 12 0 r12 c5 0 r11 0 dni rc060 3 dni remove r3, r4. place r6, r502,. rc0603 dni cc0402 dni rc0603 dni cc0402 dni r c 060 3 dni install all optional amp input components. remove c1, c2. set r3=r4=200 ohm. dni replace r5 with 0.1uf cap dni enable disable 0 enb vcm vin vip von vop ad8352 vcc gnd gnd gnd vcc rgn rdn rgp rdp dni dni dni 0 rc0402 dni rc0402 dni 06216-057 figure 53. evaluation board schematic, dut analog inputs
ad9254 rev. 0 | page 30 of 40 cc0402 cc0402 cc0805 gnd1 o2 o3 vcc1 o4 o5 gnd2 o6 o7 o8 o9 gnd3 o10 o11 vcc2 o12 o13 gnd4 o14 o15 i0 i1 gnd8 i2 i3 vcc4 i4 i5 gnd7 i6 i7 i8 i9 gnd6 i10 i11 vcc3 i12 i13 gnd5 i14 i15 oe4 oe1 o0 o1 oe3 oe2 cc0603 ad9246lfcsp d4 d5 vin- cml d2 d3 agnd avdd clk- avdd agnd avdd d6 d7 drgnd drvdd d0 (lsb) d10 avdd sense vref refb d11 d12 drgnd drvdd sdio/dcs sclk/dfs csb agnd rbias or agnd agnd d13 (msb) avdd vin+ d9 dco d8 reft clk+ pdwn d1 drgnd drvdd agnd oeb epad chip corners rc0603 output buffer output connector dut b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19 b20 j503 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 j503 7 10 22 rp501 98 rp501 22 98 rp502 22 81 22 rp500 7 10 22 rp502 6 11 22 rp502 5 12 22 rp502 4 13 22 rp502 3 14 22 rp502 2 15 22 rp502 1 16 22 rp502 6 11 22 rp501 5 12 22 rp501 4 13 22 rp501 3 14 22 rp501 2 15 22 rp501 1 16 22 rp501 4 5 rp500 22 3 6 rp500 22 2 7 rp500 22 dni r500 r0402 dni r501 r0402 10k r503 tp503 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 c20 j503 13 2 jp3 13 2 jp2 13 2 jp1 3 4 31 34 1 2 32 33 39 40 41 42 5 6 7 8 45 11 24 25 26 27 12 13 16 17 18 19 20 21 35 15 23 29 14 22 30 10 44 9 28 38 36 46 47 48 37 43 u510 jp502 dni 0.1uf c556 jp506 dni 1 3 2 jp507 dutavdd jp500 dni jp501 dni vref csb_dut e500 esnes ferv_txe dutavdd dutavdd d12 tp501 d13 dor dutdrvdd tp502 d2 dutdrvdd vref sense vin- vin+ d0 dco sclk_cha sdo_cha csb1_cha sdi_cha fifoclk fd10 fd11 fd12 fd13 d1 fifoclk fd0 fd1 fd2 fd3 fd4 fd5 fd6 fd7 fd8 fd9 fd10 fd11 fd12 fd13 fdor 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 24 1 2 3 25 48 u509 74vcx16224 d3 d4 d5 d6 d7 d8 d9 d10 d11 tp500 tp504 1.0uf c553 dutavdd clk clk d1 d9 dor d13 d12 d11 d10 d8 d7 d6 d5 d4 d3 d2 d0 dco vdl fd8 fdor fd0 fd1 fd2 fd4 fd5 fd6 fd7 fd9 fd3 cml sclk_dtp sdio_odm 0.1uf c554 0.1uf c555 06216-058 figure 54. evaluation board schematic, dut, vref, and digital output interface
ad9254 rev. 0 | page 31 of 40 smaedge smaedge r c0603 r c0603 r c0603 r c0603 r c0603 r c0603 r c0603 r c0603 cc0402 cc0402 rc0402 rc0402 rc0402 cc0402 cc0402 cc0402 rc0402 rc0402 rc0402 cc0402 rc060 3 rc0603 r c0603 cc0402 rc060 3 rc060 3 r c0603 cc0402 r c0603 r c0603 rc0603 rc0603 rc0603 rc0603 place c531,r505=0. clk/ clk xfmr/ad9515 clock circuitry ad9515 logic setup 2 1 dni r511 2 1 dni r510 opt_clk clk 0 r507 dni 0 r508 avdd_3p3v s9 2 3 5 6 7 8 9 10 11 12 13 14 15 16 25 18 19 22 23 31 32 33 u500 avdd_3p3v;1,4,17,20,21,24,26,29,30 avdd_3p3v avdd_3p3v clk opt_clk clk s1 31 2 jp508 s8 s7 s6 s5 s4 s3 s2 r514 0 dni e501 r522 0 r523 0 r524 0 r519 0 r518 0 r520 0 r521 0 r516 0 r513 0 r515 0 r517 0 r526 0 dni 240 r583 0.1uf c537 dni 240 r584 0 r509 1 3 2 d502 hsms2812 49.9 r505 dni 49.9 r504 0.1uf c531 dni 10k r588 r525 0 dni 0 r506 1 2 34 5 6 t503 0 r512 0.1uf c530 100 r585 e502 0 r575 dni 4.12k r586 r580 10k r581 dni r576 dni 0.1uf c535 dni 0.1uf c534 dni 0.1uf c536 dni c511 .1uf e503 100 r582 s9 s10 r578 dni r579 dni dni r577 0.1uf c532 0.1uf c533 s7 s8 s5 s6 s4 s3 s1 s2 s0 14 12 10 1 5 3 7 8 osc500 r527 0 dni r531 0 dni r530 0 dni r529 0 dni r528 0 dni r534 0 dni r533 0 dni r532 0 dni opt_clk s0 gnd;3,4,5 s502 gnd;3,4,5 s501 clk opt_clk to use ad9515 (opt _clk), remove r507, r508, c533, c532. 10k r587 enable disable rc0402 dni cb3lv-3c vcc out oe gnd oe gnd out vcc dni dni rc0402 dni dni rc0402 rc0402 dni nc=27,28 ad9515 clk clkb gn d gnd_pad out0 out0b out1 out1b rset s0 s1 s10 s2 s3 s4 s5 s6 s7 s8 s9 syncb vref dni rc0402 dni rc0402 dni rc0402 dni rc0402 dni s10 r c0603 r c0603 dni dni r c0603 dni r c0603 dni r c0603 dni r c0603 dni r c0603 dni r c0603 dni r c0603 dni r c0603 dni r c0603 dni 06216-059 figure 55. evaluation board schematic, dut clock input
ad9254 rev. 0 | page 32 of 40 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 nc7wz07 a1 gnd a2 y1 vcc y2 nc7wz16 a1 gnd a2 y1 vcc y2 rc0603 optional +5v=programming only=ampvdd spi circuitry gp0 picvcc gp1 for fifo controlled port, populate r555, r556, r557. when using picspi controlled port, populate r545, r546, r547. remove when using or programming pic (u506) when using picspi controlled port, remove r555, r556, r557. mc lr-gp3 +3.3v=normal operation=avdd_3p3v 1 10 2 34 56 78 9 j504 pic-header 2 4 1 3 7 6 5 3 2 8 1 4 u506 r547 4.7k dni 1 3 25 6 4 u507 1 3 25 6 4 u508 r548 10k r549 10k 1k r552 sdio_odm csb_dut sclk_dtp r553 1k r551 1k r550 10k 13 2 jp509 avdd_3p3v r554 0 r546 4.7k dni 4.7k r545 dni c557 0.1uf 12 r559 261 r558 4.7k 21 d505 e504 r557 0 r556 0 r555 0 sdo_cha csb1_cha sdi_cha sclk_cha avdd_3p3v dutavdd dni dni s1 dni dni dni dni dni header up male rc0603 cc0603 rc060 3 ddvpma v3p3_ddva dni picvcc gp1 gp0 mc lr-gp3 soic8 gp5 gp4 gp0 gp2 gp1 vss vdd mclr pic12f629 0 6216-060 figure 56. evaluation board schematic, spi circuitry
ad9254 rev. 0 | page 33 of 40 cc0603 cc0603 acase lc1210 cc0603 cc0603 cc0603 acase acase acase acase cc0603 choke_coil do-214aa 2a s2a_rect cc0603 cc0603 lc1210 lc1210 lc1210 lc1210 lc1210 cc0603 cc0603 cc0603 cc0603 gn d 1tuptuo tupni output4 lc1210 lc1210 cc0402 cc0402 cc0402 cc0402 cc0402 cc0402 cc0402 cc0402 lc1210 gn d 1tuptuo tupni output4 gn d 1tuptuo tupni output4 lc1210 gn d 1tuptuo tupni output4 smdc110f gn d 1tuptuo tupni output4 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 cc0603 cc0603 remove l501,l503,l504,l508,l509. to use optional power connection optional power connection power supply input 6v, 2a max avdd_3.3v=3.3v connected to ground mounting holes dutdrvdd=2.5v dutavdd=1.8v vdl=3.3v ground test points avdd_3p3v avdd_3p3v j505 dutdrvddin j502 dutavddin vdlin avdd_3p3v avdd_3p3v avdd_3p3vin ampvddin tp513 dutdrvdd dutavdd 0.1uf c599 c572 0.1uf r589 261 c527 10uf 2 1 cr 500 j501 tp510 1 2 3 4 5 6 7 8 9 10 p501 1 2 3 4 u502 adp3339akc-1.8 h501 tp506 vdl dutdrvdd f500 4 2 3 1 adp3339akc-3.3 u505 10uh l509 1uf c513 1 2 3 4 u501 adp3339akc-5 1 2 3 4 u504 adp3339akc-3.3 l508 10uh h503 h502 tp512 tp511 h500 tp509 c526 1uf 1uf c525 tp508 c546 0.1uf c545 0.1uf c544 0.1uf c543 0.1uf c542 0.1uf c540 0.1uf c539 0.1uf c538 0.1uf l507 10uh l506 10uh 1 2 3 4 u503 adp3339akc-2.5 0.1uf c575 0.1uf c574 0.1uf c573 0.1uf c570 l505 10uh l504 10uh l503 10uh l502 10uh l501 10uh 0.1uf c569 0.1uf c568 d504 3 4 fer500 1 2 3 p500 d503 shot_rect 3a do-214ab 0.1uf c567 c524 1uf c523 1uf c522 1uf c521 1uf c520 1uf c519 1uf c518 1uf c517 0.1uf 1ouf 6.3v c552 c516 0.1uf 1ouf 6.3v c551 c515 0.1uf 1ouf 6.3v c550 c514 0.1uf 1ouf 6.3v c549 0.1uf c566 0.1uf c565 0.1uf c564 l500 10uh c512 0.1uf 1ouf 6.3v c548 tp507 tp505 c559 0.1uf 0.1uf c558 gnd gnd ampvddin pwr_in ampvdd vdl ampvdd gnd gnd gnd vdlin pwr_in pwr_in pwr_in dutavddin dutdrvddin pwr_in pwr_in dutavdd ampvdd=5v c on005 7.5v pow er 2.5mm ja ck 06216-061 figure 57. evaluation board sc hematic, power supply inputs
ad9254 rev. 0 | page 34 of 40 evaluation board layout 0 6216-062 figure 58. evaluation board layout, primary side 0 6216-063 figure 59. evaluation board layout, secondary side (mirrored image)
ad9254 rev. 0 | page 35 of 40 0 6216-064 figure 60. evaluation board layout, ground plane 0 6216-065 figure 61. evaluation board layout, power plane
ad9254 rev. 0 | page 36 of 40 06216-066 figure 62. evaluation board layout, silkscreen primary side 06216-067 figure 63. evaluation board layout, silkscreen secondary side (mirrored image)
ad9254 rev. 0 | page 37 of 40 bill of materials table 16. evaluation board bill of materials (bom) item qty. omit (dnp) reference designator device package description supplier/part number 1 1 ad9246ce_reva pcb pcb adi 24 c1, c2, c509, c510, c511, c512, c514, c515, c516, c517, c528, c530, c532, c533, c538, c539, c540, c542, c543, c544, c545, c546, c554, c555 2 12 c3, c500, c502, c503, c504, c505, c531, c534, c535, c536, c537, c557 capacitor 0402 0.1 f 3 1 c501 capacitor 0402 0.3 pf 4 2 c4, c5 resistor 0402 0 5 10 c513, c518, c519, c520, c521, c522, c523, c524, c525, c526 capacitor 0402 1.0 f 6 1 c527 capacitor 1206 10 f 7 1 c529 capacitor 0402 20 pf 8 5 c548, c549, c550, c551, c552 capacitor acase 10 f 9 1 c553 capacitor 0805 1.0 f 10 15 c556, c558, c559, c564, c565, c566, c567, c568, c569, c570, c572, c573, c574, c575, c599 capacitor 0603 0.1 f 11 1 cr500 led 0603 green panasonic lnj314g8tra 1 d502 12 2 d500, d501 diode sot-23 30 v, 20 ma, dual schottky hsms2812 13 1 d503 diode do-214ab 3 a, 30 v, smc micro commercial components sk33- tpmsct-nd 14 1 d504 diode do-214aa 2 a, 50 v, smc micro commercial components s2a- tpmstr-nd 15 1 d505 led ln1461c amb amber led 16 1 f500 fuse 1210 6.0 v, 2.2 a trip current resettable fuse tyco, raychem nanosmdc110f-2 17 1 fer500 choke 2020 murata dlw5bsn191sq2 18 1 j500 jumper solder jumper 19 3 j501, j502, j505 jumper solder jumper 20 1 j503 connector 120 pin male header samtec tsw-140-08-g-t-ra 21 1 j504 connector 10 pin male, 2 5 samtec 22 3 jp1, jp2, jp3 jumper 3 pin male, straight samtec tsw-103-07-g-s 23 4 jp500, jp501, jp502, jp506 jumper 2 pin male, straight samtec tsw-102-07-g-s 1 jp507 24 2 jp508, jp509 jumper 3-pin jumper male, straight samtec tsw-103-07-g-s 25 10 l500, l501, l502, l503, l504, l505, l506, l507, l508, l509 ferrite bead 3.2 mm 2.5 mm 1.6 mm digikey p9811ct-nd 26 1 osc500 oscillator smt 125 mhz or 105 mhz cts reeves cb3lv-3c 27 1 p500 connector pj-102a dc power jack digikey cp-102a-nd
ad9254 rev. 0 | page 38 of 40 item qty. omit (dnp) reference designator device package description supplier/part number 28 1 p501 connector 10 pin male, straight ptmicro10 29 6 r1, r6, r563, r565, r574, r577 resistor 0402 dni 5 r2, r5, r561, r562, r571 30 6 r10, r11, r12, r535, r536, r575 resistor 0402 0 31 2 r3, r4 resistor 0402 25 32 6 r7, r8, r9, r502, r510, r511 resistor 0603 dni 33 6 r500, r501, r576, r578, r579, r581 resistor 0402 dni 34 4 r503, r548, r549, r550 resistor 0603 10 k 1 r504 35 1 r505 resistor 0603 49.9 9 r506, r508, r509, r512, r554, r555, r556, r557, r560 36 23 r507, r513, r514, r515, r516, r517, r518, r519, r520, r521, r522, r523, r524, r525, r526, r527, r528, r529, r530, r531, r532, r533, r534, resistor 0603 0 37 4 r545, r546, r547, r558 resistor 0603 4.7 k 38 3 r551, r552, r553 resistor 0603 1 k 39 1 r559 resistor 0603 261 40 2 r566, r567 resistor 0402 33 41 3 r582, r585, r598 resistor 0402 100 42 2 r583, r584 resistor 0402 240 43 1 r586 resistor 0402 4.12 k 44 3 r580, r587, r588 resistor 0402 10 k 45 1 r589 resistor 0603 261 46 2 r590, r591 resistor 0402 25 47 1 r592 resistor 0402 dni 48 2 r593, r596 resistor 0402 0 49 2 r594, r595 resistor 0402 10 k 50 1 r597 resistor 0402 4.3 k 51 1 rp500 resistor rca74204 22 52 2 rp501, rp502 resistor rca74208 22 53 1 s1 switch momentary (normally open) panasonic evq-plda15 2 s500, s501 54 2 s502, s503 connector smaedge sma edge right angle 55 2 s504, s505 connector sma200up sma rf 5-pin upright 2 t500, t501 56 1 t1 transformer sm-22 m/a-com etc1-1-13 1 t503 57 1 t502 transformer cd542 mini-circuits adt1-1wt 58 1 u500 ic 32-pin lfcsp _vq clock distribution adi ad9515bcpz 59 1 u501 ic sot-223 voltage regulator adi adp3339akcz-5
ad9254 rev. 0 | page 39 of 40 item qty. omit (dnp) reference designator device package description supplier/part number 60 1 u502 ic sot-223 voltage regulator adi adp3339akcz-1.8 61 1 u503 ic sot-223 voltage regulator adi adp3339akcz-2.5 62 2 u504, u505 ic sot-223 voltage regulator adi adp3339akcz-3.3 63 1 u506 ic 8-pin soic 8-bit microcontroller microchip pic12f629 64 1 u507 ic sc70 dual buffer fairchild nc7wz16 65 1 u508 ic sc70 dual buffer fairchild nc7wz07 66 1 u509 ic 48-pin tssop buffer/line driver fairchild 74vcx162244 67 1 u510 dut (ad9254) 48-pin lfcsp_vq adc adi ad9254bcpz 68 1 u511 (or z500) ic 16-pin lfcsp_vq differential amplifier adi ad8352acpz total 128 107
ad9254 rev. 0 | page 40 of 40 outline dimensions pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 4.25 4.10 sq 3.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicato r coplanarity 0.08 seating plane 0.25 min exposed pa d (bottom view) compliant to jedec standards mo-220-vkkd-2 figure 64. 48-lead lead frame chip scale package [lfcsp_vq] 7 mm 7 mm body, very thin quad (cp-48-3) dimensions shown in millimeters ordering guide model temperature range package description package option ad9254bcpz-150 1 , 2 C40c to +85c 48-lead lead frame chip scale package (lfcsp_vq) cp-48-3 ad9254bcpzrl7C150 1 , 2 C40c to +85c 48-lead lead frame chip scale package (lfcsp_vq) cp-48-3 ad9254-150ebz 1 evaluation board 1 z = pb-free part. 2 it is required that the exposed paddle be soldered to the agnd plane to achieve the best electrical and thermal performance. ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06216-0-10/06(0)

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